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Latest Book Reviews

Review of "Timeless Algorithms: The Foundational Ideas" by Gary Sutton

 · 17 min read

A review of the Manning early access (MEAP v5) edition of Timeless Algorithms: The Foundational Ideas by Gary Sutton, which builds each chapter around one foundational work, from Bayes in 1763 to the 2020 scaling laws. The premise is excellent and several worked examples are first-rate, but most chapters teach the textbook method instead of the work they are named for, a number of worked examples fail in their setups, the five-layer "hidden stack" framework disappears after chapter 1, and the prose needs a hard edit.
Recent
Software Ballistics Insight on Android: A Solver That Admits What It Assumed  · 17 min read projects Stalker, Part Two: Why the Trading Bot Didn't Earn Its Keep  · 13 min read Hardware The $1,175 Option: Two Questions One RISC-V Board Answered Differently  · 21 min read Hardware Reviews The SpacemiT K3 on Mainline Ubuntu: KVM Works, and the BSDs Cannot Boot  · 19 min read

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Hardware Reviews

The SpacemiT K3: RISC-V Finally Competes, and the Vendor Kernel Gets in the Way

 · 20 min read

The SpacemiT K3 Pico-ITX is the first RISC-V board on my bench that competes with ARM instead of apologising to it. It compiles Rust in 161.8 seconds, beats a Cortex-A76 on AES-GCM and SHA-256, and does 2.37 GB/s of hardware-accelerated crypto where the Pine64 Star64 manages 21.7 MB/s. It also cost $1,175.09 delivered, partitions its 16 cores into two clusters of 8 that no single process can span, and cannot run KVM at all because the vendor kernel oopses when you load the module.
Hardware Reviews

The MangoPi MQ Pro: One RISC-V Core, Two Hours, and What That Actually Proves

 · 12 min read

The MangoPi MQ Pro compiles the pinned benchmark in 7,824 seconds, two hours and ten minutes, which is 149x the fleet leader and dead last of twelve boards. But the interesting numbers are elsewhere: per core it is only 4.2x behind a SiFive U74, its 486 MB of RAM never became the bottleneck because being single-core kept peak memory to one rustc, and getting Rust onto it at all required a Debian chroot because OpenWrt is musl and rustup ships no musl-hosted compiler.
Hardware Reviews

The Pine64 Star64: RISC-V's Baseline Problem

 · 19 min read

The Pine64 Star64 runs StarFive's JH7110 - four SiFive U74 cores and an ISA string of rv64imafdc, which is RV64GC baseline and nothing more. It compiles Rust in 461 seconds, tenth of eleven on my bench, beating the Orange Pi RV2 with half the cores, matching its own JH7110 twin the Milk-V Mars to within 0.02%, and losing to a quad Cortex-A53 from 2012. On SHA-512, where nobody has hardware, it is only 5.9x behind a Cortex-A76. On AES-128-GCM it is 100x behind. That difference is the whole story - plus a hardware crypto engine sitting stranded behind missing userspace plumbing.
Hardware

Would You Pay for RISC-V? Doing the Arithmetic in Public

 · 14 min read

The worst benchmark number I ever published was an Orange Pi RV2 taking 650.60 seconds on a Rust compile that an RK3588 finishes in 52.55. I am now asking whether you would pay a monthly fee to rent RISC-V hardware from me. This is the arithmetic in public: what the SpacemiT K3 actually changed, why the one RISC-V box you can rent today implements a vector draft that was never ratified, what two nodes in a 1U at a Miami colo would really cost per month, and the strongest argument against the whole idea, which is a finding from my own build farm.
Operating Systems

Two Addresses, One Page: Finding the Firmware Bug Behind NetBSD Corruption on the Milk-V Mars

 · 16 min read

NetBSD booted on my Milk-V Mars, joined the network, and then overwrote its own kernel with pkgsrc file data under sustained write load. The evidence first pointed at a double allocation inside UVM. That diagnosis was wrong. A custom PGAUDIT kernel, a Mars-shaped QEMU target, 256 permanent canary pages, and a controlled cache-flush experiment in DDB eventually showed two physical addresses exactly 4 GiB apart reaching the same DDR backing. The unsafe 8 GiB map came from a blank EEPROM and U-Boot SPL's private memory default. This is the sequel to my original bring-up article: the wrong theories, the two device trees hiding in one boot chain, the one-line firmware correction, and the 600-second hardware A/B that contained the corruption.

Topics

Retro Computing AI & Inference Hardware Projects Philosophy Economics Systems Programming

Reading Series

8+ posts Jevons Paradox & AI Economics What happens when cognitive output gets cheaper. Demand expansion, the biological ceiling, and the AI vampire. 3 parts Heidegger & Technology Enframing, standing reserve, and what happens when AI treats specifications as raw material for code generation. 8+ posts Z80 RetroShield Running a real Z80 on modern hardware. CP/M, Forth, Zork, custom PCBs, and a dual-processor design. 3 parts Sampo CPU & Compilers A custom RISC CPU from ISA design through FPGA implementation to an LLVM backend. 6 posts Tesla P40 Home Lab Four eBay GPUs, 96GB of VRAM, and every workload we can throw at them. LLMs, TTS, video generation. 3 parts The Lattice Language A programming language where mutability is a phase transition. Novel type system, bytecode VM, 100 opcodes.
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Written by Alex Jokela Software engineer by trade, tinkerer by nature, single-board computer hoarder by choice. More about me →